New Contributor
New ContributorYes. I have applied that patch. Without that, Quartus hangs.
Super ContributorMay I know does your problem had been resolved using the patch?
If not, possible copy the full error message for database searching.
New ContributorUnfortunately not. I will send you more information on Friday.
best
SAH
New ContributorThis is what I get:
And if you open "Preview Report":
See the file "Error.txt" to see the error message.
I also attached the whole build log in BuildReport.txt.
Please let me know if you need more information.
Best,
Ali
Super ContributorI can't find the database. Could you try latest version 26.1?
Could you try re-generate the jesd ip?
Could you also provide minimum project which can duplicate the issue? Else, it'll be difficult to debug
New ContributorThere is a custom IP in our design that is not compatible with Quartus 26.1. I regenerated the JESD IP, but this did not resolve the issue.
However, I noticed that reducing the bit resolution of the our DSP module (from 54 bits to 39 bits) allows the design to compile successfully. More specifically, the design contains several large arrays of std_logic_vector. When I reduce both the array size and the width of its elements, the project compiles without the fatal error. The total size of the arrays is less than 100k bits, so I would not expect this to cause any memory-related issues. For reference, the same DSP design has previously compiled successfully using Vivado and Quartus 24.1 on Windows, as mentioned earlier.
Does this information help identify the root cause? Otherwise, I would try to create a minimal example to help isolate the issue.
