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binupr's avatar
binupr
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Quartus optimising out big bunches of logic

Hi there, In my project, I noticed Quartus is optimising a lot of sub-module components in synthesis. Interesting thing is when I run the sub-module synthesis, its components are in tact. How can I...
Hdl
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

Anything not connected eventually to an I/O can get optimized away. You can use virtual pin assignments to unconnected signals to avoid this.