quartus_map ended unexpectedly 12.0 sp2 upgrade

Hi,

I encoutered internal Q12 crash relating to a missing .cdf file of the TSE IP. Altera support did not find the reason causing it. Finally, after many different tries (removal of db and internal_db directories and other stuffs), the solution was to delete the TSE in SOPC Builder and regenerate the same one.

Good luck.

The problem came back today; the only clue is this error message.

Error (293007): Current module quartus_fit ended unexpectedly

Removing the db, incremental_db, and also the synthesis subdirectory for the QSYS network subsystem hasn't managed to resolve the issue.

Problem came back, and deleting all of the various intermediate files is no longer showing any improvement in the situation. Its odd because designs which compiled before now fail with this message.

Error (293007): Current module quartus_fit ended unexpectedly

Should I interpret this result to indicate the the design doesn't fit?

Is there any way to further diagnose the situation?

You cannot interpret this as your design does not fit but as Quartus fitter crashes

due to a particular point in your design.

Take into account the compilation messages just before the crash wich could point to the block wich cause the issue.

Temporaly change or separate this block from the rest of the design and relaunch the compilation.

If you are using ALTERA megafunctions (NIOS, TSE, FIFO, PLL, ALTDDIO etc...) be sure they are all upgrade with the current release of Quartus (you can see that in the Analysis report => IP).

Thanks pantxoa for that suggestion, I will look into that.

For completeness, here is a possibly unrelated Quartus crash that occurred when I attempted another compile of the same design yesterday evening.

p, li { white-space: pre-wrap; } Internal Error: Sub-system: SCI, File: /quartus/sld/sci/sci_opencore_spec_reader.cpp, Line: 1342

The required design file timedDataSys/synthesis/submodules/altera_tse_top_gen_host.v is missing

Stack Trace:

0x507e7: SCI_OPENCORE_FILE_PARSER::parse_file(char const*, char const*, bool) + 0x10e9 (sld_sci)

0x510a2: SCI_OSR_PPE::SCI_OSR_PPE(char const*, char const*, char const*, bool) + 0x828 (sld_sci)

0xfcd91: SGN_EXTRACTOR::register_ocp_entity(unsigned long, _Dinkum_std::basic_string<char, _Dinkum_std::char_traits<char>, MEM_STL_ALLOCATOR<char> >, FIO_PATH, char const*) + 0x231 (synth_sgn)

0xfeb2f: SGN_EXTRACTOR::register_ocp_entity(unsigned long, HDB_ENTITY*) + 0x10f (synth_sgn)

0x1cebf4: SGN_EXTRACTOR::recurse_into_newly_extracted_netlist(HDB_ENTITY*, HDB_INSTANCE_NAME*, unsigned long, SGN_WRAPPER_INFO*) + 0x104 (synth_sgn)

0x1c75ca: SGN_EXTRACTOR::recursive_extraction(HDB_INSTANCE_NAME*, SGN_WRAPPER_INFO*, char const*) + 0xb6a (synth_sgn)

0x1cf52a: SGN_EXTRACTOR::recurse_into_newly_extracted_netlist(HDB_ENTITY*, HDB_INSTANCE_NAME*, unsigned long, SGN_WRAPPER_INFO*) + 0xa3a (synth_sgn)

0x1c75ca: SGN_EXTRACTOR::recursive_extraction(HDB_INSTANCE_NAME*, SGN_WRAPPER_INFO*, char const*) + 0xb6a (synth_sgn)

0x1cf52a: SGN_EXTRACTOR::recurse_into_newly_extracted_netlist(HDB_ENTITY*, HDB_INSTANCE_NAME*, unsigned long, SGN_WRAPPER_INFO*) + 0xa3a (synth_sgn)

0x1c75ca: SGN_EXTRACTOR::recursive_extraction(HDB_INSTANCE_NAME*, SGN_WRAPPER_INFO*, char const*) + 0xb6a (synth_sgn)

0x1cf52a: SGN_EXTRACTOR::recurse_into_newly_extracted_netlist(HDB_ENTITY*, HDB_INSTANCE_NAME*, unsigned long, SGN_WRAPPER_INFO*) + 0xa3a (synth_sgn)

0x1c75ca: SGN_EXTRACTOR::recursive_extraction(HDB_INSTANCE_NAME*, SGN_WRAPPER_INFO*, char const*) + 0xb6a (synth_sgn)

0x1cf52a: SGN_EXTRACTOR::recurse_into_newly_extracted_netlist(HDB_ENTITY*, HDB_INSTANCE_NAME*, unsigned long, SGN_WRAPPER_INFO*) + 0xa3a (synth_sgn)

0x1c75ca: SGN_EXTRACTOR::recursive_extraction(HDB_INSTANCE_NAME*, SGN_WRAPPER_INFO*, char const*) + 0xb6a (synth_sgn)

0x1cf52a: SGN_EXTRACTOR::recurse_into_newly_extracted_netlist(HDB_ENTITY*, HDB_INSTANCE_NAME*, unsigned long, SGN_WRAPPER_INFO*) + 0xa3a (synth_sgn)

0x1c75ca: SGN_EXTRACTOR::recursive_extraction(HDB_INSTANCE_NAME*, SGN_WRAPPER_INFO*, char const*) + 0xb6a (synth_sgn)

0x1cfc59: SGN_EXTRACTOR::extract() + 0x369 (synth_sgn)

0x1d005d: sgn_qic_full(CMP_FACADE*, _Dinkum_std::vector<_Dinkum_std::basic_string<char, _Dinkum_std::char_traits<char>, MEM_STL_ALLOCATOR<char> >, MEM_STL_ALLOCATOR<_Dinkum_std::basic_string<char, _Dinkum_std::char_traits<char>, MEM_STL_ALLOCATOR<char> > > >&, _Dinkum_std::vector<double, MEM_STL_ALLOCATOR<double> >&) + 0x13d (synth_sgn)

0x28f30: qsyn_execute_sgn(CMP_FACADE*, _Dinkum_std::vector<_Dinkum_std::basic_string<char, _Dinkum_std::char_traits<char>, MEM_STL_ALLOCATOR<char> >, MEM_STL_ALLOCATOR<_Dinkum_std::basic_string<char, _Dinkum_std::char_traits<char>, MEM_STL_ALLOCATOR<char> > > >&, _Dinkum_std::basic_string<char, _Dinkum_std::char_traits<char>, MEM_STL_ALLOCATOR<char> > const&) + 0x180 (quartus_map)

0x40e33: QSYN_FRAMEWORK::execute_core() + 0xc3 (quartus_map)

0x4138f: QSYN_FRAMEWORK::execute() + 0x11f (quartus_map)

0x1aeef: qexe_do_normal(QEXE_FRAMEWORK*, char const*) + 0x1bd (comp_qexe)

0x1b5ed: qexe_standard_main(QEXE_FRAMEWORK*, QEXE_OPTION_DEFINITION const**, int, char const**) + 0x491 (comp_qexe)

0x27c6b: qsyn_main(int, char const**) + 0x9b (quartus_map)

0x1fb58: msg_main_thread(void*) + 0x18 (ccl_msg)

0x5b58: thr_final_wrapper + 0xe (ccl_thr)

0x21c42: msg_thread_wrapper(void* (*)(void*), void*) + 0x72 (ccl_msg)

0x6b981: mem_thread_wrapper(void* (*)(void*), void*) + 0xd1 (quartus_map)

0x9b30: err_thread_wrapper(void* (*)(void*), void*) + 0x2a (ccl_err)

0x5b8b: thr_thread_wrapper + 0x2f (ccl_thr)

0x33d01: msg_exe_main(int, char const**, int (*)(int, char const**)) + 0xb7 (ccl_msg)

0x1538f: main + 0x4f (quartus_map)

0x19113: __libc_start_main + 0xf3 (c.so.6)

End-trace

Quartus II 32-bit Version 12.0 Build 263 08/02/2012 SJ Full Version

Service Pack Installed: 2

Its interesting that there appear to be two triple speed ethernet IP in use (one with caps in its name and one with underscores in its name)

Altera altera_merlin_multiplexer 12.0 N/A 205

Altera altera_avalon_sgdma 12.0 N/A 206

Altera altera_avalon_sgdma 12.0 N/A 207

Altera triple_speed_ethernet 12.0 N/A 208

Altera Triple Speed Ethernet N/A May 2012 209

Altera altera_merlin_demultiplexer 12.0 N/A 210

Altera altera_merlin_demultiplexer 12.0 N/A 211

Altera Nios II Processor (6AF7_00A2) N/A Apr 2009 212

Altera altera_avalon_mm_bridge 12.0 N/A 213

Altera altera_avalon_sc_fifo 12.0 N/A 214

FWIW, when opening all of the subsystems in QSYS and attempting to regenerate them after they updated to new IP components I saw this failure when regenerating one of them. In the past it has been possible to specify the clock frequency external to the QSYS subsystem.

"/home/hill/altera/12.0/quartus/linux/jre/bin/java" -Xmx512M -classpath "/home/hill/altera/12.0/quartus/sopc_builder/bin/sopc_builder.jar:/home/hill/altera/12.0/quartus/sopc_builder/bin/PinAssigner.jar:/home/hill/altera/12.0/quartus/sopc_builder/bin/sopc_wizard.jar:/home/hill/altera/12.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"/home/hill/altera/12.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpath/tmp/alt5577_6994878190239698345.dir/0014_sopclgen --no_splash --refresh /tmp/alt5577_6994878190239698345.dir/0014_sopclgen/yysystem.v --quartus_dir="/home/hill/altera/12.0/quartus" --sopc_perl="/home/hill/altera/12.0/quartus/linux/perl" --sopc_lib_path="++/home/hill/altera/12.0/quartus/../ip/altera/sopc_builder_ip+/home/hill/altera/12.0/quartus/../ip/altera/nios2_ip"

Info: Finished elaborating classic module.

Executing: /home/hill/altera/12.0/quartus//sopc_builder/bin/sopc_builder --classic --generate /tmp/alt5577_6994878190239698345.dir/0014_sopclgen/yysystem.ptf

Info: Running sopc_builder...

"/home/hill/altera/12.0/quartus//linux/jre/bin/java" -Xmx512M -classpath "/home/hill/altera/12.0/quartus//sopc_builder/bin/sopc_builder.jar:/home/hill/altera/12.0/quartus//sopc_builder/bin/PinAssigner.jar:/home/hill/altera/12.0/quartus//sopc_builder/bin/sopc_wizard.jar:/home/hill/altera/12.0/quartus//sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"/home/hill/altera/12.0/quartus//sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpath/tmp/alt5577_6994878190239698345.dir/0014_sopclgen --generate /tmp/alt5577_6994878190239698345.dir/0014_sopclgen/yysystem.v --quartus_dir="/home/hill/altera/12.0/quartus/" --sopc_perl="/home/hill/altera/12.0/quartus//linux/perl" --sopc_lib_path="++/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip+/home/hill/altera/12.0/quartus//../ip/altera/nios2_ip"

.

WARNING:

Clock yyclock_clk does not have a clock frequency at /home/hill/altera/12.0/quartus//sopc_builder/bin/europa/europa_utils.pm line 248.

ERROR:

positive-number required for log2 not (0)

Error: Generator program

for module 'timedDataPeriph_sys_clk_timer' did NOT run successfully.

generator cmd was '/home/hill/altera/12.0/quartus//linux/perl/bin/perl -I/home/hill/altera/12.0/quartus//sopc_builder/bin -I/home/hill/altera/12.0/quartus//sopc_builder/bin/europa -I/home/hill/altera/12.0/quartus//sopc_builder/bin/perl_lib -I/tools/perl/5.8.8/linux32/lib/5.8.8/i686-linux-thread-multi -I/tools/perl/5.8.8/linux32/lib/5.8.8 -I/tools/perl/5.8.8/linux32/lib/site_perl/5.8.8/i686-linux-thread-multi -I/tools/perl/5.8.8/linux32/lib/site_perl/5.8.8 -I/tools/perl/site-lib -I. -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_timer -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_pio -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -I/home/hill/altera/12.0/quartus//../ip/altera/nios2_ip/altera_nios_custom_instruction -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_burst_adapter -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_mutex -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_cf -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_spi -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_pipeline_bridge -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_user_defined_interface -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_sopc_builder -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_cfi_flash -I/home/hill/altera/12.0/quartus//../ip/altera/nios2_ip/altera_nios_dev_board_stratix_2s60_rohs -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_pll -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_sgdma -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_adapter_upstream_pipeline -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_epcs_flash_controller -I/home/hill/altera/12.0/quartus//../ip/altera/nios2_ip/altera_nios_dev_kit_stratix_edition_sram -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_lan91c111 -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_adapter_downstream_pipeline -I/home/hill/altera/12.0/quartus//../ip/altera/nios2_ip/altera_nios_dev_kit_stratix_edition_sram2 -I/home/hill/altera/12.0/quartus//../ip/altera/nios2_ip/altera_nios_dev_board_stratix_1s40 -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_uart -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_clock_adapter -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_adapter_waitrequest_pipeline -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_adapter_slave_y -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_mailbox -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_asmi -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/amd_avalon_am29lv065d_flash -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_adapter_master_y -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_endian_adapter -I/home/hill/altera/12.0/quartus//../ip/altera/nios2_ip/altera_nios_dev_board_cyclone_1c20 -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_tri_state_bridge -I/home/hill/altera/12.0/quartus//../ip/altera/nios2_ip/altera_nios_dev_board_stratix_1s10_es -I/home/hill/altera/12.0/quartus//../ip/altera/nios2_ip/altera_nios_dev_board_cyclone_2c35 -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/no_legacy_module -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_cy7c1380_ssram -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/amd_avalon_am29lv128m_flash -I/home/hill/altera/12.0/quartus//../ip/altera/nios2_ip/altera_nios2 -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_cs8900 -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_performance_counter -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_sysid -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_fifo -I/home/hill/altera/12.0/quartus//../ip/altera/nios2_ip/altera_nios_dev_board_stratix_2s60_es -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_timer -I/home/hill/altera/12.0/quartus//../ip/altera/nios2_ip/altera_nios_multiply -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_dma -I/home/hill/altera/12.0/quartus//../ip/altera/nios2_ip/altera_nios_dev_board_stratix_1s10 -I/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_clock_crossing -I/home/hill/altera/12.0/quartus//../ip/altera/nios2_ip/altera_nios_dev_board_stratix_2s60 /home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_timer/em_timer.pl --system_name=yysystem --target_module_name=timedDataPeriph_sys_clk_timer --system_directory=/tmp/alt5577_6994878190239698345.dir/0014_sopclgen --sopc_directory=/home/hill/altera/12.0/quartus//sopc_builder --sopc_lib_path=/tmp/alt5577_6994878190239698345.dir/0014_sopclgen+/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip+/home/hill/altera/12.0/quartus//../ip/altera/nios2_ip+/home/hill/altera/12.0/quartus//sopc_builder/components --generate=1 --verbose=0 --software_only=0 --module_lib_dir=/home/hill/altera/12.0/quartus//../ip/altera/sopc_builder_ip/altera_avalon_timer --sopc_quartus_dir=/home/hill/altera/12.0/quartus/ --projectname=yysystem.qpf'

Info: sys_clk_timer: "timedDataPeriph" instantiated altera_avalon_timer "sys_clk_timer"

Error: Generation stopped, 25 or more modules remaining

Info: timedDataPeriph: Done timedDataPeriph" with 17 modules, 1 files, 124481 bytes

Error: Error writing sopcinfo report java.lang.IllegalArgumentException: Setting 'LOAD_VALUE' value of -1 (0x-1) doesn't fit in an unsigned 64-bit constant

Error: Error writing html report java.lang.IllegalArgumentException: Setting 'LOAD_VALUE' value of -1 (0x-1) doesn't fit in an unsigned 64-bit constant

Error: ip-generate failed with exit code 1: 4 Errors, 5 Warnings

Info: Finished: Create HDL design files for synthesis

Loading each of the subsystems in QSYS and saving/regenerating them hasn't changed the result seen for the version of each component.

Altera altera_merlin_multiplexer 12.0 N/A N/A 205

Altera altera_avalon_sgdma 12.0 N/A N/A 206

Altera altera_avalon_sgdma 12.0 N/A N/A 207

Altera triple_speed_ethernet 12.0 N/A N/A 208

Altera Triple Speed Ethernet N/A May 2012 Licensed 209

Altera altera_merlin_demultiplexer 12.0 N/A N/A 210

Altera altera_merlin_demultiplexer 12.0 N/A N/A 211

Altera Nios II Processor (6AF7_00A2) N/A Apr 2009 Licensed 212

Altera altera_avalon_mm_bridge 12.0 N/A N/A 213

Altera altera_avalon_sc_fifo 12.0 N/A N/A 214

Altera altera_avalon_sc_fifo 12.0 N/A N/A 215

Altera altera_avalon_sc_fifo 12.0 N/A N/A 216

Altera altera_merlin_master_agent 12.0 N/A N/A 217