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Baller's avatar
Baller
Icon for New Contributor rankNew Contributor
1 year ago
Solved

Quartus Lite 'No paths found'

I am currently working on a KISS2 to verilog translator and this is one of the designs that it generated cannot measure FMax. My verilog module consists of 3 blocks: - state transitions (choosing...
Hdl
  • FvM's avatar
    FvM
    1 year ago

    O.k., you didn't show the registered part of your design.

    Problem is however, that your state logic is creating latches by incompletely decoding states, which breaks timing analysis of states register. To remove latches, preset nextstate to current state:

    always @(*) //1st process (transitions)
  begin
    nextstate = states;
    case(states)
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
1 year ago

I can only give a general answer. Latches must be avoided in synchronous logic design, the most simple way is to make default assignments in combinational always blocks for all variables that are not obviously assigned under all conditions. They don't hurt (and don't consume any logic resources) if they are redundant. They'll of course break intentional latches which should never happen in a reasonable design.

Baller's avatar
Baller
Icon for New Contributor rankNew Contributor
1 year ago

Thank you

Some of the files I generate implement this rule, giving extra reliability to the design (those safe designs I mentioned) and those never encountered this latch problem. I suppose my main goal of testing and comparing all the possible designs was still reached and now I can see that for some FSM 3 process description style without default assignments is just fundamentally flawed