Forum Discussion
New ContributorQuartus Lite 'No paths found'
O.k., you didn't show the registered part of your design.
Problem is however, that your state logic is creating latches by incompletely decoding states, which breaks timing analysis of states register. To remove latches, preset nextstate to current state:always @(*) //1st process (transitions) begin nextstate = states; case(states)
Super ContributorHi,
Fmax calculation works only for registered (edge sensitive) logic with a dedicated clock. It's assessing the longest combinational path between two register. To determine overall design speed, you might add in- and output registers and specify the clock input with create_clock in .sdc file.
BallerHi
Thanks for replying, I was going to update the post with more information about the design but I'll include it here:The module is an FSM automatically generated from the KISS2 file and I do not wish to change it drastically. The entire file consists of 3 modules:
1 - determining next state
2- determining the current output
3- memory handling (assigning nextstate to state)
This is how it looks like:module train11_DOut (
input reset, clk,
input [1:0] in,
output reg [0:0] out);reg [3:0] states, nextstate;
parameter [3:0]
st0 = 0,
st1 = 1,
st2 = 2,
st3 = 3,
st4 = 4,
st5 = 5,
st6 = 6,
st7 = 7,
st8 = 8,
st9 = 9,
st10 = 10;always @(*) //1st process (transitions)
begin
case(states)
st0: casex(in)
2'b00: nextstate = st0;
2'b10: nextstate = st1;
2'b01: nextstate = st2;
endcase
st1: casex(in)
2'b10: nextstate = st1;
2'b00: nextstate = st3;
2'b11: nextstate = st5;
endcase
st2: casex(in)
2'b01: nextstate = st2;
... (other state transitions) ...
endalways@(*) //2nd process (outputs)
begin
out = 1'b1;
case(states)
st0: casex(in)
2'b00: out = 1'b0;
endcase
endcase
endalways @(posedge clk) //3rd process (clock)
begin
if (reset)
states <= st0;
else
states <= nextstate;
end
endmoduleMy SDC file consists only of 1GHz clock creation for clk
I am completely new to the subject and I am not sure how I could force a timing calculation without changing the module code, but my research so far leads me to believe I will have to. Any and all feedback is appriciated because I am starting to get desperate
