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Hi,
weird thing. I'm trying to assign wires to each other, and quartus is doing it in reverse !
for example (Verilog)
wire [9:0] a;
wire [0:-9] b;
when I do: assign a=b, I get that a is reversed b,
i.e. if a="1110001010" then b is "0101000111"
this is definitely not how Verilog works, is it a bug in quartus ?!
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Normally when you say a="1110001010", it means (from right to left) a[0]=0, a[1]=1, a[2]=0,... a[9]=1. This means the bit at the most left is the MSB. Most computer software will read the "a" vector as a number and always place the MSB at the left regardless of your Verilog declaration. Are you sure that's not the case?
Your post is unclear as it does not specify the bitfields of "b".
Check individual bits separately (b[-9], b[-8] and so on) and see if they are correct.
Because of the way the vectors are declared in this case, the correct way Verilog should "work" when you do 'assign a=b', is like this:
a[0] = b[-9]
a[1] = b[-8]
a[2] = b[-7]
...
a[9] = b[0]
If you're getting something different, the it's a bug in Quartus.
Honored Contributor
