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Altera_Forum
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13 years ago

Quartus is flipping bits when negative range is used ?!

Hi, weird thing. I'm trying to assign wires to each other, and quartus is doing it in reverse ! for example (Verilog) wire [9:0] a; wire [0:-9] b; when I do: assign a=b, I get tha...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

the entire design is written as a pixed-point DSP,

so... [3:-9] means 4 bits for integer, 9 bits for fractional.

that's the design, that's how verilog works.

The problem, is that I'm using filters that Matlab generated, and they use the "traditional" notation (the [9:0] one...), so the filter gets the bits in reverse.

but now I see the bug is only in SignalTap way of displaying the numbers, they are not reversed when I open the busses and compare bit to bit.

only as a group