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Altera_Forum's avatar
Altera_Forum
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10 years ago

Quartus Instantiated megafunction and then synthesized away

Hi,

In my project i have instantiated more than one VHDL unit that realize a moving average filter. During Analysis and Synthesis i found that only for one i have the following info messages:

Info (19000): Inferred 1 megafunctions from design logic

Info (276034): Inferred altshift_taps megafunction from the following design logic: "IN_BLOCK:U4|FILTERS:U1|moving_avg:FILT|\ma_gen:reg_data[0][13]_rtl_0"

Info (12133): Instantiated megafunction "IN_BLOCK:U4|FILTERS:U1|moving_avg:FILT|altshift_taps:\ma_gen:reg_data[0][13]_rtl_0" with the following parameter:

Info (12134): Parameter "NUMBER_OF_TAPS" = "1"

Info (12134): Parameter "TAP_DISTANCE" = "8"

Info (12134): Parameter "WIDTH" = "126"

Info (12134): Parameter "POWER_UP_STATE" = "DONT_CARE"

And then i receive this warning:

Warning (14285): Synthesized away the following RAM node(s):

Warning (14320): Synthesized away node "IN_BLOCK:U4|FILTERS:U1|moving_avg:FILT|altshift_taps:\ma_gen:reg_data[0][13]_rtl_0|shift_taps_mev:auto_generated|altsyncram_1jc1:altsyncram4|ram_block7a84"

As a consequence all my logic that depends on the above unit is synthesized away.

I use Quartus 13.1

Thanks for your help

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    I've seen this happen during development when something is instantiated but nothing else depends on it. If this is the case with your second instance, hooking it up to it's I/O should cause it to not be optimized away.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    The output of the instance is used in many part of the design. I receive this warning when i have added new logic that depends on it. However if i made some errors on the new logic, the old logic should still use the output being synthesized away and Quartus should keep them.

    I don't know why all the logic that depends on the output is synthesized away.

    Another thing is:

    The output synthsized away is part of a custom record type. Is it possible that Quartus remove all the record through the design just because one element is synthesized away?
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Quartus will remove logic when it determines that it has no effect on an IO pin at all. It will have nothing to do with your custom record type (as I have previously said). There will be a problem somewhere with your design.

    Does the logic connect to IO pins? Are some inputs constants?

    Without seeing the project, we can only speculate as the the problems. Quartus has NO problems with record types (other than expanding them out in RTL/tech viewer) as I have used them and seen them used for years without problems. Quartus can even cope with some esoteric design.

    The problem will be your design, not your code.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    The strange thing is that in the RTL viewer all is present and correctly connected but in the Technology map viewer a good part of the design is gone

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Until you post code or a .qar of the project, we cannot help much.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Ok i found the problem. There was a comparator with the max and min thershold constant (generics) inverted (the max threshold was lower than the min threshold) so the comparation is not synthesizable. This caused a domino effect on the entire project.

    Thanks to all for your help.