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Altera_Forum's avatar
Altera_Forum
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10 years ago

Quartus Instantiated megafunction and then synthesized away

Hi, In my project i have instantiated more than one VHDL unit that realize a moving average filter. During Analysis and Synthesis i found that only for one i have the following info messages: ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

The strange thing is that in the RTL viewer all is present and correctly connected but in the Technology map viewer a good part of the design is gone