Honored ContributorI am using mega function wizard to generate a two port RAM for my design. Please see the attached picture of the 2-port RAM that I generated.
When I simulate it, I give my address input on the rising edge of read clock, data output is delayed by two clock cycles. But I expect my data output in the next clock cycle. How do I achieve it?. Am I missing something? Please advice.
Honored ContributorMaybe you have registered input and output?
2 clock cycles is better for timing constraints (throughput is about the same during bursts) if signals have to travel a lot into chip for high frequency designs.Honored ContributorYou can see in the picture that you posted that the RAM is configured with both the inputs and outputs registered (see the little flip-flop symbols driven by the clock). This explains your 2-clock delay. I believe the input registers are always there, but the output registers are optional. Walk through the settings in the Megawizard and you should see a check box that will allow you to eliminate the output registers.
Honored ContributorThank you flz47655, and rsefton. It works now!
