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Altera_Forum
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10 years ago

Quartus II_Version 13.0- --RAM Megafunction- Timing Issue

I am using mega function wizard to generate a two port RAM for my design. Please see the attached picture of the 2-port RAM that I generated. When I simulate it, I give my address input on the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Maybe you have registered input and output?

2 clock cycles is better for timing constraints (throughput is about the same during bursts) if signals have to travel a lot into chip for high frequency designs.