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Altera_Forum's avatar
Altera_Forum
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11 years ago

Quartus II v14, Qsys - VHDL not generated - generates verilog instead

Although I select to create VHDL outputs in the gui, only verilog is generated. I also see in the log that --verilog is used. Seems like the GUI doesn't forward the command to the shell commands correctly :

Info: ip-generate --project-directory="C:\Altera Projects" --output-directory="C:\Altera Projects\nios2_2nd_trial\synthesis" --file-set=QUARTUS_SYNTH --report-file="html:D:\Altera Projects\nios2_2nd_trial\nios2_2nd_trial.html" --report-file="sopcinfo C:\Altera Projects\nios2_2nd_trial.sopcinfo" --report-file="cmp C:\Altera Projects\nios2_2nd_trial\nios2_2nd_trial.cmp" --report-file="qip C:\Altera Projects\nios2_2nd_trial\synthesis\nios2_2nd_trial.qip" --report-file="svd C:\Altera Projects\nios2_2nd_trial\synthesis\nios2_2nd_trial.svd" --report-file="regmap C:\Altera Projects\nios2_2nd_trial\synthesis\nios2_2nd_trial.regmap" --report-file="xml C:\Altera Projects\nios2_2nd_trial\nios2_2nd_trial.xml" --report-file="debuginfo C:\Altera Projects\nios2_2nd_trial\synthesis\nios2_2nd_trial.debuginfo" --report-file="greybox C:\Altera Projects\nios2_2nd_trial\greybox\nios2_2nd_trial.v" --system-info=DEVICE_FAMILY="Cyclone IV GX" --system-info=DEVICE=EP4CGX15BF14A7 --system-info=DEVICE_SPEEDGRADE=7 --component-file="C:\Altera Projects\nios2_2nd_trial.qsys" --language=vhdl

...

Info: onchip_memory2_0: Generation command is [exec C:/tools/altera/quartusii/quartus/bin64/perl/bin/perl.exe -I C:/tools/altera/quartusii/quartus/bin64/perl/lib -I C:/tools/altera/quartusii/quartus/sopc_builder/bin/europa -I C:/tools/altera/quartusii/quartus/sopc_builder/bin/perl_lib -I C:/tools/altera/quartusii/quartus/sopc_builder/bin -I C:/tools/altera/quartusii/quartus/../ip/altera/sopc_builder_ip/common -I C:/tools/altera/quartusii/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/tools/altera/quartusii/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios2_2nd_trial_onchip_memory2_0 --dir=C:/Users/dss/AppData/Local/Temp/alt6276_5569204388560648074.dir/0023_onchip_memory2_0_gen/ --quartus_dir=C:/tools/altera/quartusii/quartus --verilog --config=C:/Users/dss/AppData/Local/Temp/alt6276_5569204388560648074.dir/0023_onchip_memory2_0_gen//nios2_2nd_trial_onchip_memory2_0_component_configuration.pl --do_build_sim=0 ]

I attached the tcl file for the Qsys project for reference - just trying to instantiate a Nios2 with a timer and a couple of RAMs.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    I *think* the issue is; --file-set=QUARTUS_SYNTH

    For synthesis Quartus handles any combination of languages (VHDL+Verilog+AHDL), so ip-generate generates the synthesis source in whatever format it comes in.

    For simulation, Modelsim-ASE can only handle one language, eg., VHDL or Verilog (VHDL + encrypted SystemVerilog also seems to be acceptable), so if you run ip-generate for simulation, then I think --language=VHDL will be respected.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Thanks :-)

    I believe this was just a beginner-issue; looking in the wrong places for the vhdl file ;-) The generator generates both synthesis and simulation HDL files, and I was looking in the synthesis folder for what I wanted - found it in the simulation/submodules folder. Case closed..