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Altera_Forum's avatar
Altera_Forum
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11 years ago

Quartus II v14, Qsys - VHDL not generated - generates verilog instead

Although I select to create VHDL outputs in the gui, only verilog is generated. I also see in the log that --verilog is used. Seems like the GUI doesn't forward the command to the shell commands corr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Thanks :-)

I believe this was just a beginner-issue; looking in the wrong places for the vhdl file ;-) The generator generates both synthesis and simulation HDL files, and I was looking in the synthesis folder for what I wanted - found it in the simulation/submodules folder. Case closed..