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Altera_Forum's avatar
Altera_Forum
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11 years ago

Quartus II v14, Qsys - VHDL not generated - generates verilog instead

Although I select to create VHDL outputs in the gui, only verilog is generated. I also see in the log that --verilog is used. Seems like the GUI doesn't forward the command to the shell commands corr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I *think* the issue is; --file-set=QUARTUS_SYNTH

For synthesis Quartus handles any combination of languages (VHDL+Verilog+AHDL), so ip-generate generates the synthesis source in whatever format it comes in.

For simulation, Modelsim-ASE can only handle one language, eg., VHDL or Verilog (VHDL + encrypted SystemVerilog also seems to be acceptable), so if you run ip-generate for simulation, then I think --language=VHDL will be respected.

Cheers,

Dave