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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Quartus II TCL: Analyze vhd files in a directory using quartus_map executable

Hello,

I would like to analyze specific vhd files in a directory, not all of the design files (as part of an incremental compilation flow).

I tried to use --analyze_file option of the quartus_map executable but it seems not to like a list as argument. 

  
  ...
  set filename_list 
  if {} {
   ...
  } else {
   ...
  }

So i tried a foreach loop to execute the module for each file, it's working but it's redundant and slow.

Is there a better way to do it please?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    The following appears to work for me, if what you are aiming for is to only analyse the file for syntax and or logic errors.

    quartus_map --64bit --no_banner not_a_project --family="xxx" --part=yyy --set=HDL_INTERFACE_OUTPUT_PATH=./test_compile --generate_hdl_interface=zzz.vhd --source=zzz.vhd

    I learned how to do this by looking at what the analyse files button in the QSYS component editor does.