Quartus II TCL: Analyze vhd files in a directory using quartus_map executable

The following appears to work for me, if what you are aiming for is to only analyse the file for syntax and or logic errors.

quartus_map --64bit --no_banner not_a_project --family="xxx" --part=yyy --set=HDL_INTERFACE_OUTPUT_PATH=./test_compile --generate_hdl_interface=zzz.vhd --source=zzz.vhd

I learned how to do this by looking at what the analyse files button in the QSYS component editor does.