Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorQuartus II TCL: Analyze vhd files in a directory using quartus_map executable
Hello, I would like to analyze specific vhd files in a directory, not all of the design files (as part of an incremental compilation flow). I tried to use --analyze_file option of the quar...
Altera_ForumHonored Contributor
Honored ContributorThe following appears to work for me, if what you are aiming for is to only analyse the file for syntax and or logic errors.
quartus_map --64bit --no_banner not_a_project --family="xxx" --part=yyy --set=HDL_INTERFACE_OUTPUT_PATH=./test_compile --generate_hdl_interface=zzz.vhd --source=zzz.vhd I learned how to do this by looking at what the analyse files button in the QSYS component editor does.
