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Altera_Forum's avatar
Altera_Forum
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8 years ago

Quartus II Simulation Waveform Problem

Hi everyone, I am an undergraduate student currently having Final Year Project on FPGA design.

I encountered a problem while trying to simulate the design in Quartus II Simulation Waveform.

I had followed this tutorial step by step:

ftp://ftp.altera.com/up/pub/intel_material/14.1/tutorials/verilog/quartus_ii_simulation.pdf

However, the pop up box shows the error Failed to access library './rtl_work' at "./rtl_work"

I am using Quartus II 14.1 Web Edition and Modelsim-Altera 10.3c.

I had also tried to launch the simulation in Modelsim by navigating to Tools > Run simulation tools > RTL Simulation in Quartus, but the same error message appears in Modelsim...

Does anyone faced the same issue as me?

Please help me.

Thank you.:-P

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    Hi, thank you for replying.

    It turned out that I need to add "\" at the end of the directory of my Modelsim-Altera under the EDA Tool Options...

    I can simulate the .v verilog file now.

    However, when i try to simulate the ALTFP_DIV in the IP catalog, this error occurs in Modelsim...

    Instantiation of 'lpm_mult' failed. The design unit was not found.

    The same goes to lpm_add_sub, lpm_compare and altsyncram.

    Any idea on how to solve this problem?

    Thank you.
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    Hi,

    Are you manually loading the file to Modelsim or using script generated?

    Follow the tcl script instruction which is generated in Modelsim directory.

    Best Regards,

    Anand Raj Shankar

    (This message was posted on behalf of Intel Corporation)
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    I simulate by navigating to Tools > Run Simulation Tools > RTL Simulation.

    I had also already selected appropriate EDA Tools Settings as attached.

    When the Modelsim pop up, it can compile without problem.

    However, when I simulate my testbench, that error shows up...
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    Attached are the files that i am trying to simulate.

    My steps are as follow, please correct me if I am wrong:

    1. Create a .bdf file.

    2. Insert the ALTFP_DIV module, give it the name division, generate the symbol file in the end of the MegaFunction Wizard.

    3. Insert the block generated in step 2 to the .bdf file, assign all the IO pins to the block.

    4. From the .bdf file, generate top.v file by going to File > Create/Update > Generate HDL Design File from Current File.

    5. Exclude the .bdf file, include the top.v file, division.v file and testbench.v file.

    6. In Assignment > Setting > EDA Tool Setting > Simulation, select compile test bench and add my testbench file (testbench.v).

    7. At Tools > Options > EDA Tool Option, specify my modelsim-altera directory (C:\altera\14.1\modeilsim_ase\win32aloem\).

    8. Tools > Run Simulation Tools > RTL Simulation.

    Thank you.
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    --- Quote Start ---

    Hi,

    I have tried to simulate the ALTFP_DIV it was successful.

    Check the steps and compilation order

    Can you share the hierarchy of your project ?

    Check the files attached

    https://www.alteraforum.com/forum/attachment.php?attachmentid=14788

    Best Regards,

    Anand Raj Shankar

    (This message was posted on behalf of Intel Corporation)

    --- Quote End ---

    Hi Mr Anand Raj Shankar,

    I noticed that you have answered many posts about similar issue like mine and you are able to simulate them well.

    If possible, can you please guide us through your steps in simulating the Altera IP module?

    It is very much appreciated if you are able to.

    Thank you.
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    Hi,

    Apologies for the delay.

    Following steps are required to set the environment.

    1.Under NativeLink settings, select the Compile test bench option, and then click the Test Benches button.

    2. Click New. Specify testbench_1 as the Test bench name, and tb as the Top level module in test bench.

    3. Under Test bench and simulation files, enter or select the testbench_1.v file, click Add, and then click OK. The Test Benches dialog box displays the properties of the testbenches in your project.

    Refer

    https://www.altera.com/en_us/pdfs/literature/ug/ug_gs_msa_qii.pdf

    Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

    Best Regards,

    Anand Raj Shankar

    (This message was posted on behalf of Intel Corporation)