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Altera_Forum
Honored Contributor
8 years agoAttached are the files that i am trying to simulate.
My steps are as follow, please correct me if I am wrong: 1. Create a .bdf file. 2. Insert the ALTFP_DIV module, give it the name division, generate the symbol file in the end of the MegaFunction Wizard. 3. Insert the block generated in step 2 to the .bdf file, assign all the IO pins to the block. 4. From the .bdf file, generate top.v file by going to File > Create/Update > Generate HDL Design File from Current File. 5. Exclude the .bdf file, include the top.v file, division.v file and testbench.v file. 6. In Assignment > Setting > EDA Tool Setting > Simulation, select compile test bench and add my testbench file (testbench.v). 7. At Tools > Options > EDA Tool Option, specify my modelsim-altera directory (C:\altera\14.1\modeilsim_ase\win32aloem\). 8. Tools > Run Simulation Tools > RTL Simulation. Thank you.