Honored ContributorHi,
It was odd enough to find that after compile, the resource utilisation showed zero usage, timing report showed 'no path to report'. However when I opened the RTL viewer I could see that something pretty complex was synthesised there. Why would this happen and how to fix it? btw, when I removed two FIFOs, everything got back to normal. Thanks!
Honored ContributorRTL viewer is mainly what you write in your HDL before optimizations occur(I have seen a few optimizations show up in the RTL viewer). So, for example, if you didn't hook up your clock, you could have a 100K LE design in the RTL viewer that then gets synthesized down to nothing in the chip. Comb through the synthesis messages and report. There's a section named something like "Optimizations that trigger other optimizations, which is another good place to look at". One other old trick is to add partitions randomly in the hierarchy. This preserves boundaries, so the partition that gets synthesized out is the culprit.
Honored ContributorHi,
Do you figure your question out? I have the same question with you except "no path to report". Can you please me some tips? Thanks
