Quartus ii resource utilization showed all zero usage

RTL viewer is mainly what you write in your HDL before optimizations occur(I have seen a few optimizations show up in the RTL viewer). So, for example, if you didn't hook up your clock, you could have a 100K LE design in the RTL viewer that then gets synthesized down to nothing in the chip. Comb through the synthesis messages and report. There's a section named something like "Optimizations that trigger other optimizations, which is another good place to look at". One other old trick is to add partitions randomly in the hierarchy. This preserves boundaries, so the partition that gets synthesized out is the culprit.