Hello, I recently installed the latest Quartus II 8.0 SP1 and I am trying to get familiar with the tool. I have few questions I couldn't find an answer in the tutorials or by searching. 1. How I can generate a VHDL instantiation template? The File->Create/Update->Create VHDL Component... does only the component declaration. 2. I created a minimal test design with two VHDL files , one of them being the top module. What I noticed is that "Analyze Current File" always analyzes both of them,no mather which one I am currently working on. Why? I did not instantiated (yet) the second module in the top entity. 3. How I can generate a test bench template for a file other than the top module? (Simulation tool: Modelsim-Altera) Processing->Start->Start Test Bench Template Writer always generates the test bench for the top module. General comments. I thought this tool would be a friendly one. But I find important commands or options deeply hidden under misleading menus and hard to use. But maybe it's just me, being new with Quartus. Thanks! BR

Hi, 1. I couldn't find, either. Probably there is no such template. 2. Are these files shown in the file list, which is located Project->Add/Remove Files... 3. You can change the top module in your project from General categoly in the setting dialog box. Once you set any module as a top, you can create testbench for it. I hope this answer can help. Thanks,

1) You need to have a VHDL file open in Quartus Use Edit->Insert Template->Constructs->Design Units-> Entity and Edit->Insert Template->Constructs->Design Units-> Architecture To generate a VHDL entity and architecture 2) Are you certain you are not seeing messages relating to the component instantiation rather than actucal analysis of the sub module? 3) You could try temporarily making the sub-module the top level and making a testbench for that. Hope this helps a bit

Thank you gee, 1. Well, there is "Create Verilog Instantiation Template" under the same menu. Why not VHDL too? So, when you have a complex component with many pins how do you instantiate it? You manually type it? 2. Both files are present in Project-> Add remove files. 3. Yes, true. But this is weird...

Hi vernmid, Thank you for the answer. 1. This is not what I want. I want an instantiation template for my component, not a generic, empty one. 2. I have quite good VHDL experience. I don't have any error in my files actually. But when I deliberately introduce an error in one file (like one line containing the "-" only), save it, then go to the other file and click Analyze Current File, it gives me the error for the other file (which is not current!) 3. Yes, thank you. I don't think this is how it should be!

Hi, 1. It is inconvenient but ... 2. Don't you try to remove the file you don't want to elabolate?

Quartus II newbie questions | Altera Community

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Altera_Forum
Honored Contributor
17 years ago
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The best way to help is to discuss about what was asked and provide a solution or work around if possible.
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Well let's try this again.

1st question:

--- Quote Start ---
1. How I can generate a VHDL instantiation template? The File->Create/Update->Create VHDL Component... does only the component declaration.
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From Quartus beginning at the edit menu:
a - Edit->Insert Template->VHDL->Constructs->Design Units->Entity. Does this menu exist in the web edition of the software and if so does it meet your needs?
In my subscription edition it creates the following:
entity <entity_name> is generic ( <name> : <type> := <default_value>; ... <name> : <type> := <default_value> ); port ( -- Input ports <name> : in <type>; <name> : in <type> := <default_value>; -- Inout ports <name> : inout <type>; -- Output ports <name> : out <type>; <name> : out <type> := <default_value> ); end <entity_name>;

2nd Question:

--- Quote Start ---
2. I created a minimal test design with two VHDL files , one of them being the top module. What I noticed is that "Analyze Current File" always analyzes both of them,no mather which one I am currently working on. Why? I did not instantiated (yet) the second module in the top entity.
--- Quote End ---

When I click on the "Analyze Current File" button on the left side of the text editor window (I normally use an external editor so this is new to me), It only analyzes the currently open file and no others. Here is the processing output in Quartus:
Info: ******************************************************************* Info: Running Quartus II Analyze Current File Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version Info: Processing started: Wed Oct 29 17:29:43 2008 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off trio_top -c trio_top --analyze_file=C:\Projects\cvs_test\trio\fpga\X2\trio_top\src\sdi\sdi_top.v Info: Quartus II Analyze Current File was successful. 0 errors, 0 warnings Info: Peak virtual memory: 155 megabytes Info: Processing ended: Wed Oct 29 17:29:44 2008 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01

Can you post the output you get in the web edition?

Jake
Altera_Forum
Honored Contributor
17 years ago
1.

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In my subscription edition it creates the following:
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Thank you, this is indeed a work around for the question I asked. But, honestly, it is faster for me to type it and copy/paste ports than going through a 6 levels menu+trees just to get an example about how it should look like.
2.

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Can you post the output you get in the web edition?
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Sure, here:
Info: ******************************************************************* Info: Running Quartus II Analyze Current File Info: Version 8.0 Build 215 05/29/2008 SJ Web Edition Info: Processing started: Wed Oct 29 19:58:27 2008 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off test1 -c test1 --analyze_file=R:\altera\test1\hdl_src\my_and.vhd Error (10500): VHDL syntax error at test1.vhd(11) near text "-"; expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration" Error (10523): Ignored construct test1 at test1.vhd(12) due to previous errors Error: Quartus II Analyze Current File was unsuccessful. 2 errors, 0 warnings Error: Peak virtual memory: 166 megabytes Error: Processing ended: Wed Oct 29 19:58:29 2008 Error: Elapsed time: 00:00:02 Error: Total CPU time (on all processors): 00:00:02
I am posting this from home where I have 8.0 without SP1 but I get the same from 8.0 with SP1 at work.
Please notice that the analyze was started with my_and.vhd and it found an error in test1.vhd.
test1 is not instantiated in my_and and is a separate file.
The reported error is what I deliberately introduced to show the problem.
test1 is also the name of the test project in which test1.vhd is the top entity.
In your report, from what I can see, you started the analyze with the top module and of course, it reported that everything is OK. How about introducing an error in the top module and start the analyze on a sub module?
BR

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