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Altera_Forum's avatar
Altera_Forum
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9 years ago

Quartus II generates empty tdf file, then fails

Hi,

when I try to synthesize my design in Quartus II 15.0 the process fails with the error "Text Design File must contain a Subdesign and Logic Section". The file name is 
cmpr_xxx.tdf
where xxx is a sequence of three characters that is different each time I try to synthesize.

The file only contains the following comment 

--lpm_compare CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_WIDTH=5 ONE_INPUT_IS_CONSTANT="YES" ageb dataa datab
--VERSION_BEGIN 15.0 cbx_cycloneii 2015:04:22:18:04:07:SJ cbx_lpm_add_sub 2015:04:22:18:04:07:SJ cbx_lpm_compare 2015:04:22:18:04:07:SJ cbx_mgl 2015:04:22:18:06:50:SJ cbx_stratix 2015:04:22:18:04:08:SJ cbx_stratixii 2015:04:22:18:04:08:SJ  VERSION_END
-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, the Altera Quartus II License Agreement,
--  the Altera MegaCore Function License Agreement, or other 
--  applicable license agreement, including, without limitation, 
--  that your use is for the sole purpose of programming logic 
--  devices manufactured by Altera and sold by Altera or its 
--  authorized distributors.  Please refer to the applicable 
--  agreement for further details.
--VALID FILE

but nothing else.

I have already tried to delete all auto-generated Quartus file and restarted the compilation process.

What could be the reason that Quartus generates an empty tdf file in the first place?

Thanks a lot for your suggestions,

David

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    --- Quote Start ---

    when I try to synthesize my design...

    --- Quote End ---

    What is your design source? You imply Quartus is generating the (empty) AHDL files, but from what? Or is this AHDL file contain your design source?

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Hi Alex,

    thanks for your reply. My design source is a Qsys system. I haven't added the AHDL file manually. I assume it is generated by Quartus as it is located in the "db" folder of my project and is regenerated when I delete this folder and restart compilation. Additionally, its file name changes every time. I tried to understand where this component is required and I think it is used in the ALTSHIFT_TAPS component as shown in the following screenshot

    https://www.alteraforum.com/forum/attachment.php?attachmentid=12212

    I also regenerated the associated IP core FShiftReg but without success.
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    So, your Qsys system is the only entity in your design and is your top level? What file(s) have you added to your Quartus project?

    Qsys, by default, generates verilog source files, not AHDL. If you have captured your design entirely within Qsys then, having saved and generated your system, you need only add the <my_qsys_system>.qsys file to your Quartus project.

    You mention the "db" folders - you shouldn't be digging around in there. These are temporary files that Quartus uses/creates. They never contain design source that you need to add to your Quartus project.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    --- Quote Start ---

    So, your Qsys system is the only entity in your design and is your top level? What file(s) have you added to your Quartus project?

    --- Quote End ---

    Basically, yes. It's a design for Cyclone V so there is some additonal peripheral stuff for the hard processor system.

    --- Quote Start ---

    You mention the "db" folders - you shouldn't be digging around in there. These are temporary files that Quartus uses/creates. They never contain design source that you need to add to your Quartus project.

    --- Quote End ---

    Ususally, I leave this folder alone. But the error orginiates from there: it contains the empty AHDL file. I certainly haven't added this file manually, but it is generated by Quartus.
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    If you're still having problems...

    Copy 3 files - .qpf, .qsf & .qsys - to a new directory and open the Quartus project there.

    Open Qsys and the .qsys file. Generate HDL.

    Once completed, try running the project through Quartus.

    If that still fails then I suggest you post those three files here.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Dear Alex

    thanks for your message. After repeatedly deleting and regenerating some of the auto-generated files the design compiled. Unfortunately, I could not reproduce what exact step caused the compilation process to fail. I will keep your suggestion in mind in case the problem occurs again.

    Regards,

    David
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Hi,

    I have the same issue about a tdf empty file generated by Quartus at the main compilation process during "Analysis & Synthesis" compilation.

    Error (287035): Text Design File must contain a Subdesign and Logic Section

    Error (12006): Node instance "add_sub2" instantiates undefined entity "add_sub_msd"

    To be clear :

    - I'm using Quartus 14.0.0.200

    - My project is for 5CSXFC6C6U23C7 Cyclone V SoC

    - The main part is under one Qsys design with HPS

    - Only 2 IPs are under top level with the QSys IP (SDI II and Reconfig that do not exist under QSys)

    - I'm using about a dozen of DSPBuilder IP that I wrapped in QSys custom IPs (mainly with Avalon-ST and Avalon-MM links)

    - I'm using some others VHDL IP that I also wrapped in QSys IPs.

    - The main source code files, "*.mdl" for DSPBuilder ones and VHDL ones, are listed in Quartus project files. QSys use only wrappers to the main source code. It is the only mean I found to compil many DSPBuilder IPs in the same project.

    - IMPORTANT THING : the same code compiled on other computer is OK.

    - I solved the problem one time with installing again Quartus 14, but this time after reinstall it's not working

    So all my project was OK, the compilation process was OK and my system worked very well.

    When I tried my last DSPBuilder IP, I integrate it and it was working but not in external RAM exchange. I saw that I was wrong when I make the custom QSys IP, I have chosen SYMBOL burst count unit instead of WORD count unit. So I changed it, I updated my design with F5 key, and Generated HDL again.

    After that, such a correction always worked fine. But when I launch the compilation process it stop with this error.

    First I do not connect a previous error to this problem but it could be linked :

    Before this error, QSys seemed badly generate the HDL with missing VHDL files in its HDL directory, that produce a first error of missing files in Quartus compilation. After cleaning compilation directories, and generate again the HDL in QSys, it seemed OK but not the main compilation.

    I tried to compare the Quartus directories files to find a corrupted file, but without success !

    As my source code is under SVN I tried to start another clean directory with only the source code. With the same Quartus I have the same error. On another computer with the same Quartus 14.0.0.200 it's OK.

    What's wrong ??? Please give me a clue !