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Altera_Forum's avatar
Altera_Forum
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15 years ago

Quartus II can't find package during synthesis

Hi all!

In a design I am currently working on, I need to manually instanciate a Stratix IV I/O buffer.

So here is my code: 


library stratixiv;
use stratixiv.stratixiv_components.all;
    a_in : stratixiv_io_ibuf
    generic map
    (
        differential_mode   => "false",
        bus_hold            => "false",
        lpm_type            => "stratixiv_io_ibuf"
    )
    port map
    (
        i                   => a,
        o                   => a_int
    );

This works fine in simulation (ModelSIM DE 6.6a), but during synthesis with Quartus II 10.1 I get the following error:

--- Quote Start ---

Error (10481): VHDL Use Clause error at ns_io.vhd(26): design library "stratixiv" does not contain primary unit "stratixiv_components" File: /home/ns/ns_io/src/ns_io.vhd Line: 26

Error (10800): VHDL error at ns_io.vhd(26): selected name in use clause is not an expanded name File: /home/ns/ns_io/src/ns_io.vhd Line: 26

Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings

Error: Peak virtual memory: 330 megabytes

Error: Processing ended: Thu Apr 28 13:23:30 2011

Error: Elapsed time: 00:00:08

Error: Total CPU time (on all processors): 00:00:07

--- Quote End ---

I could find the package file stratixiv_components.vhd several time:

/opt/altera10.1/modelsim_ase/altera/vhdl/src/stratixiv/stratixiv_components.vhd

/opt/altera10.1/quartus/eda/fv_lib/vhdl/stratixiv/stratixiv_components.vhd

/opt/altera10.1/quartus/eda/sim_lib/stratixiv_components.vhd

/opt/altera10.1/quartus/libraries/vhdl/wysiwyg/stratixiv_components.vhd

I could fix this by removing the use clause at the beginnning of my file and adding the file /opt/altera10.1/quartus/eda/synthesis/stratixiv.vhd to the sources of the project, but this is not clean.

any idea on why the package is not found during synthesis?

Thx,

-Julien

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    for whatever reason Quartus doesn't like use stratixiv.stratixiv_components.all; but use stratixiv.all; seems to work. i chose to turn it off for synthesis, simulation will still pick up the library

    other than that it looks like you just need a component declaration for the I/O buffer. this works: 

    library ieee;
use ieee.std_logic_1164.all;
-- synthesis translate_off 
library stratixiv;
use stratixiv.stratixiv_components.all;
-- synthesis translate_on
entity test_io is
	port 
	(
		a	   : in std_logic;
		b          : out std_logic
	);
end entity;
architecture rtl of test_io is
	 COMPONENT  stratixiv_io_ibuf
	 GENERIC 
	 (
		bus_hold	:	STRING := "false";
		differential_mode	:	STRING := "false";
		simulate_z_as	:	STRING := "Z";
		lpm_type	:	STRING := "stratixiv_io_ibuf"
	 );
	 PORT
	 ( 
		dynamicterminationcontrol	:	IN STD_LOGIC := '0';
		i	:	IN STD_LOGIC := '0';
		ibar	:	IN STD_LOGIC := '0';
		o	:	OUT STD_LOGIC
	 ); 
	 END COMPONENT;
begin
    a_in : stratixiv_io_ibuf
    generic map
    (
        differential_mode   => "false",
        bus_hold            => "false",
		  simulate_z_as       => "Z",
        lpm_type            => "stratixiv_io_ibuf"
    )
    port map
    (
        dynamicterminationcontrol => '0',
        i                   => a,
		  ibar                => open,
        o                   => b
    );
end rtl;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thx but actually what we try to do is to avoid declaring components, that's why we want to use the package.