Forum Discussion
Altera_Forum
Honored Contributor
14 years agofor whatever reason Quartus doesn't like use stratixiv.stratixiv_components.all; but use stratixiv.all; seems to work. i chose to turn it off for synthesis, simulation will still pick up the library
other than that it looks like you just need a component declaration for the I/O buffer. this works:library ieee;
use ieee.std_logic_1164.all;
-- synthesis translate_off
library stratixiv;
use stratixiv.stratixiv_components.all;
-- synthesis translate_on
entity test_io is
port
(
a : in std_logic;
b : out std_logic
);
end entity;
architecture rtl of test_io is
COMPONENT stratixiv_io_ibuf
GENERIC
(
bus_hold : STRING := "false";
differential_mode : STRING := "false";
simulate_z_as : STRING := "Z";
lpm_type : STRING := "stratixiv_io_ibuf"
);
PORT
(
dynamicterminationcontrol : IN STD_LOGIC := '0';
i : IN STD_LOGIC := '0';
ibar : IN STD_LOGIC := '0';
o : OUT STD_LOGIC
);
END COMPONENT;
begin
a_in : stratixiv_io_ibuf
generic map
(
differential_mode => "false",
bus_hold => "false",
simulate_z_as => "Z",
lpm_type => "stratixiv_io_ibuf"
)
port map
(
dynamicterminationcontrol => '0',
i => a,
ibar => open,
o => b
);
end rtl;