Quartus II apparently doesn't automatically use the simulation testfile that was made for a 4 to 1 Mux and its already in the VHDL file put in In- and output declarations to simulate input data without manually presetting the in-and outputs first?

What tool are you using for simulation? If it's ModelSim, the testbench should be a separate file, not included with the design itself.

If you're using the old built-in simulation tool of Quartus, you need a .vwf file for the testbench.

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