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Altera_Forum's avatar
Altera_Forum
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12 years ago

QUARTUS II - Design with sfixed input pins (?)

Hello.

Why Quartus II design file (.BDF) does not acept in/out pins be sfixed?

ex:

entity entidade is

port(

x1: in sfixed (4 downto -5);

x2: in sfixed (4 downto -5);

x3: in sfixed (4 downto -5);

rst: in std_logic;

clk: in std_logic;

en_in: in std_logic;

output: out sfixed (4 downto -5));

end entity entidade;

Is there any way to work with fixed point as input and output in the design with quartus II?

Thanks.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    yes - dont use BDF files, and stick with HDL instead.

    BDF requires you to use std_logic_vectors only.

    Ive not tried using sfixed/ufixed at the top level for pin assignment - Im not sure how it would handle the -ve indices. You can safely use std_logic_vector, signed and unsigned perfectly fine though.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Interesting, but I need to pass numbers like 0,875 (binary 0,111) as inputs, and probably taking some fixed point as output.

    A ten bit signed would be 1000000001 (-1) with std_logic_vector, but waht if we need to represent 0,111?

    Thanks Tricky.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    a std_logic_vector is not a number - its just a collection of bits. it is also similar to sfixed in that it is an array of std_logic.

    1.5 in a fixed point would be "0110" in 4.2 notation. As a a std_logic_vector, it would be "0110" also (its just an array of bits). Similarly, in an unsigned type, it would also be "0110". The only difference is that the sfixed contains the power information via the +ve (integer part) and -ve (fraction) in it's indeces. For the other types you need to keep track of where the separation lies.

    the fixed_pkg has a to_slv function that will return a std_logic_vector of the correct length.

    NOTE: 1000000001 in signed is -1023, not -1 (its twos compliment).
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    a std_logic_vector is not a number - its just a collection of bits. it is also similar to sfixed in that it is an array of std_logic.

    1.5 in a fixed point would be "0110" in 4.2 notation. As a a std_logic_vector, it would be "0110" also (its just an array of bits). Similarly, in an unsigned type, it would also be "0110". The only difference is that the sfixed contains the power information via the +ve (integer part) and -ve (fraction) in it's indeces. For the other types you need to keep track of where the separation lies.

    the fixed_pkg has a to_slv function that will return a std_logic_vector of the correct length.

    NOTE: 1000000001 in signed is -1023, not -1 (its twos compliment).

    --- Quote End ---

    Very well explained. Thanks Tricky.