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Altera_Forum
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12 years ago

QUARTUS II - Design with sfixed input pins (?)

Hello. Why Quartus II design file (.BDF) does not acept in/out pins be sfixed? ex: entity entidade is port( x1: in sfixed (4 downto -5); x2: in sfixed (4 downto -5); x3:...
Altera_Forum's avatar
Altera_Forum
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12 years ago

yes - dont use BDF files, and stick with HDL instead.

BDF requires you to use std_logic_vectors only.

Ive not tried using sfixed/ufixed at the top level for pin assignment - Im not sure how it would handle the -ve indices. You can safely use std_logic_vector, signed and unsigned perfectly fine though.