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Altera_Forum
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12 years ago

QUARTUS II - Design with sfixed input pins (?)

Hello. Why Quartus II design file (.BDF) does not acept in/out pins be sfixed? ex: entity entidade is port( x1: in sfixed (4 downto -5); x2: in sfixed (4 downto -5); x3:...
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Altera_Forum
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12 years ago

Interesting, but I need to pass numbers like 0,875 (binary 0,111) as inputs, and probably taking some fixed point as output.

A ten bit signed would be 1000000001 (-1) with std_logic_vector, but waht if we need to represent 0,111?

Thanks Tricky.