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trynhard
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1 year ago

Quartus Freezes at a Certain Percent While Compiling

Hello everyone, I am a new user of Quartus and am trying to compile my very first VHDL project. I am using the latest version of the Quartus 23.1. I have designed a very simple 2-input AND gate with...
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trynhard's avatar
trynhard
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1 year ago

It actually doesn't matter how long I wait. I once waited for hours and it was still stuck at the same percent in Analysis&Synthsis. I expand the Analysis&Synthesis and I observe no errors, etc. Just in system messages, I see "Warning (262004): Ignoring Signal Tap instance "auto_signaltap_0" with signal set none" Other than that, I see no warning, error. I am targeting Cyclone V. Thanks