Forum Discussion
Occasional Contributorquartus disable automatic delay compensation
So you're talking about the Optimize Hold Timing setting. Delay is added to meet hold timing at the expense of some setup slack. Assignments menu -> Settings -> Compiler Settings -> Advanced Fitter Settings.
Super ContributorNo. Delay is inherent to signals reaching their destination so you cannot remove these delays. I think you're misinterpreting "simulation" here. For a functional simulation to verify the design is working functionally, yes, delays are not taken into account. It just looks at how the logic itself functions (i.e. make sure a 1 ANDed with another signal going high produces a 1).
The idea behind timing analysis to to make sure that a receiving/latch register correctly latches in data, based on the register's setup and hold timing requirements, which is inherent to the silicon. As such, the delays for when the clocks arrive at the launch and latch registers as well as the data delay to get the data from the launch register to the latch register are required for such an analysis.
While more difficult to set up and it takes much longer to run (and it's not supported for every device), a gate-level simulation (in a 3rd party simulation tool) does test functionality and does take data delays into account. Between an RTL functional simulation and timing analysis, you fully verify your design while avoiding having to perform a gate-level sim.
GOMEZ_IT
I think I explained myself poorly. I noticed that during compilation quartus has the ability to insert delays on the data and clock lines. I'm not sure how he manages to insert them, but he does it to try to close the timing. If I define via sdc for example "set input delay max/min" assuming that there is an external device that launches the data towards the fpga, quartus appropriately adds delays on the data/clock to be able to latch the data correctly. I was wondering if it was possible to eliminate this correction function..
