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KennyT_altera's avatar
KennyT_altera
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1 month ago

Quartus 20.1std compilation fails for Quartus map - Device 10AS057K2F40I1SG

Hi Chandu sri,  We will continue the discussion here. Issue Chandu Sri is facing compilation errors in Quartus when working with the Arria 10 device (10AS057K2F40I1SG/10AS057K2F40I1HG) and HPS I...
Compilation
chandu_sri's avatar
chandu_sri
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7 days ago

Hi Richard,

Sorry, I am missing to check the altera community forum. looks like as it is failing to create hps IP it is not reflected in .qar file, could you please try to create an HPS IP core from your end and see if the errors I shared earlier are replicated.

Thanks,

Chandu sri

RichardT_altera's avatar
RichardT_altera
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6 days ago

Pasting the error here for reference and tracking:

Warning: krpi_hps.arria10_hps_0: HPS model no longer supports simulation for HPS FPGA Bridges.
Warning: krpi_hps.arria10_hps_0: This module has no ports or interfaces
Info: Platform Designer Tip: Please Sync All System Infos before attempting to resolve the following error messages
Error: krpi_hps.arria10_hps_0: Unsupported device 10AS057K2F40I1HG
Error: krpi_hps: list element in quotes followed by ":" instead of space
   while executing
"foreach {pad_id ball_name } $location_map {
                             set pad_name "PAD_${pad_id}"
                             set pad_to_ball_name($pad_name) $ball_name
                             #send_message info " $pad_na..."
   (procedure "elab_io_interface_signals" line 36)
   invoked from within
"elab_io_interface_signals $peripheral_name $mode_value peripheral_ports"
   (procedure "elab_FPGA_Peripheral_Signals" line 123)
   invoked from within
"elab_FPGA_Peripheral_Signals $device_family"
   (procedure "elab" line 60)
   invoked from within
"elab 1"
   (procedure "compose_logicalview" line 7)
   invoked from within
"compose_logicalview"
Error: krpi_hps.arria10_hps_0: "Counter for GPIO debouncer" (CONFIG_HPS_DIV_GPIO) 0 is out of range: 1-65535
Error: krpi_hps.arria10_hps_0: "Sugested peripherial PLL VCO frequency" (PERI_PLL_AUTO_VCO_FREQ) 0 is out of range: 320-3000


I do not see this error on my side. Could you confirm whether this error occurs during the Platform Designer Generate HDL process?
I’ve attached a simple design for you to test it out.

Regards,
Richard Tan