Quartus 18.1 - ModelSim Starter 10.5b - IP-Core LPM_MULT (square) problems

I try to simulate a design with a LPM_MULT IP-Core in square mode. I'm able to compile the design but the simulator fails with the following error message:

Error: (vsim-3389) mul_sqr.v(53): Port 'sclr' not found in the connected module (6th connection).

The relevant content of the verilog file looks like this:

    altsquare      altsquare_component ( 
 
                               .aclr (aclr), 
 
                               .clock (clock), 
 
                               .data (dataa), 
 
                               .result (sub_wire0), 
 
                               .ena (1'b1), 
 
                               .sclr (1'b0));

If i remove the "sclr"-Line the simulation works. It looks like the IP-Core is not properly generated.

Any help would be greatly appreciated.