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Luca
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5 years ago

[Quartus 17.0] Internal Error: Sub-system: CCLK, File: /quartus/periph/cclk/cclk_gen5_base.cpp, Line

Hello there, I'm trying to add a second external clock source to a design implemented on a DE10-Standard Kit. I'd like to use the J14/HSMC_CLKIN0 pin as single-ended clock source actually, then use...