Quartus 12.1 Verilog bug: $signed() with >>> operation is ineffective.

Thanks sstrell and FvM for mentioning. Ya, it can be either way like below.

First:

module test(

input wire signed [31:0] in,

input wire [4:0] shift_amount,

input wire signext,

output wire signed [31:0] out

);

assign out = signext ? (in >>> shift_amount) : (in >> shift_amount);

endmodule

Second:

module test(

input wire [31:0] in,

input wire [4:0] shift_amount,

input wire signext,

output wire signed [31:0] out

);

assign out = signext ? ($signed(in) >>> shift_amount) : ($signed(in) >> shift_amount);

endmodule