Forum Discussion
bionukg
New Contributor
New ContributorQuartus 12.1 Verilog bug: $signed() with >>> operation is ineffective.
module test(
input wire [31:0] in,
input wire [4:0] shift_amount,
input wire signext,
output wire [31:0] out
);
assign out = signext ? ($signed(in) >>> shift_amount) : (in >> shift...
FvM
Super Contributor
Super ContributorThere's no need for $signed(), neither in must be signed. Operation of arithmetic shift is solely determined by result signedness.
sstrellSuper Contributor
Super ContributorThat's what I was thinking originally. Just the fact that >>> is used would preserve the sign bit by shifting in 1's if it's 1.
