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bionukg's avatar
bionukg
Icon for New Contributor rankNew Contributor
2 years ago

Quartus 12.1 Verilog bug: $signed() with >>> operation is ineffective.

module test( input wire [31:0] in, input wire [4:0] shift_amount, input wire signext, output wire [31:0] out ); assign out = signext ? ($signed(in) >>> shift_amount) : (in >> shift...
Compilation
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

So why is $signed still needed if in is already signed in this code? I don't see the need for $signed at all.

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    2 years ago
    There's no need for $signed(), neither in must be signed. Operation of arithmetic shift is solely determined by result signedness.
    • sstrell's avatar
      sstrell
      Icon for Super Contributor rankSuper Contributor
      2 years ago

      That's what I was thinking originally. Just the fact that >>> is used would preserve the sign bit by shifting in 1's if it's 1.