Quartus 12.1 Verilog bug: $signed() with >>> operation is ineffective.

Hi,

Based on the statement provided by FvM, have to do modification to the code like below:

module test(

input wire signed [31:0] in,

input wire [4:0] shift_amount,

input wire signext,

output wire signed [31:0] out

);

assign out = signext ? ($signed(in) >>> shift_amount) : (in >> shift_amount);

endmodule

RTL viewer:

Thanks,

Best regards,

Sheng