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bionukg's avatar
bionukg
Icon for New Contributor rankNew Contributor
2 years ago

Quartus 12.1 Verilog bug: $signed() with >>> operation is ineffective.

module test( input wire [31:0] in, input wire [4:0] shift_amount, input wire signext, output wire [31:0] out ); assign out = signext ? ($signed(in) >>> shift_amount) : (in >> shift...
Compilation
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

Why do you even need $signed here? If you're using arithmetic shift right (>>>) it would automatically shift in 1's to maintain the sign if the MSB is 1.

And also realize that Quartus 12.1 is now a 12 year old version of the tool. Have you tried anything more recent?

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago
It's no bug.

IEEE 1800-2017, 11.4.10 Shift operators specifies:
The arithmetic right shift shall fill the vacated bit positions with zeros if the result type is unsigned. It shall fill the vacated bit positions with the value of the most significant (i.e., sign) bit of the left operand if the result type is signed. (...) The result signedness is determined by the left-hand operand and the remainder of the expression, as outlined in 11.8.1.

As the result type in example is unsigned, the observed behaviour is correct.