Quartus 10.0 SystemVerilog syntax highlighting

the GUI had significant changes from 9.1 to 10.0, something could have gotten lost in the shuffle. you might want to file an SR for a bug report.

if you post a code example here i can confirm (i don't use SV)

 
module syntax;
    logic var_1;  // SystemVerilog : logic should be highlighted
    reg var_2;  // Verilog : reg is highlighted
endmodule

If the above code is in a SystemVerilog (*.sv) file the reg keyword will be highlighted but the logic keyword will not. Quartus 10.0 doesn't have a problem compiling SystemVerilog. So it looks like they just forgot add in SV keywords to their keyword list.

Over all the 10.0 GUI does seem better than 9.1 but syntax highlighting is important for an IDE.

Thanks for your help. I will file a bug report if I can't figure this out in a day or two.

thanks

i confirm highlighting in 9.1 but not 10.0