Quartus 10.0 SystemVerilog syntax highlighting

 
module syntax;
    logic var_1;  // SystemVerilog : logic should be highlighted
    reg var_2;  // Verilog : reg is highlighted
endmodule

If the above code is in a SystemVerilog (*.sv) file the reg keyword will be highlighted but the logic keyword will not. Quartus 10.0 doesn't have a problem compiling SystemVerilog. So it looks like they just forgot add in SV keywords to their keyword list.

Over all the 10.0 GUI does seem better than 9.1 but syntax highlighting is important for an IDE.

Thanks for your help. I will file a bug report if I can't figure this out in a day or two.