Forum Discussion

New Contributor

2 years ago

Quartus , Platform Designer, TSE IP

Hello, I have quarus 24.1 version and trying design Ethernet SGMII interface. I am trying use TSE IP. First i like generate example design , but keep getting error bellow. Is there way generate e...

Platform

paveetirrasrie_Altera

Frequent Contributor

1 year ago

Hi,

Based on the error, looks like some IP configuration error.

Kindly follow the steps mentioned in User Guide to generate the example design and let me know if you faced similar error.

https://www.intel.com/content/www/us/en/docs/programmable/683402/22-4-21-1-0/design-walkthrough.html

Regards,

pavee

Forum Discussion

Quartus , Platform Designer, TSE IP

Recent Discussions

Quartus Prime Lite 25.1 - Issue with the Verilog generate loops

Quarus Prime Installer 24.1 - Error SSL Certificate, Curlcde : 60

getting a licnese

ModelSim Intel FPGA Ed. 2020.1 not updating changes to HDL File

Number of ports required for a floating license