Honored ContributorAs you find workarounds to Qsys issues please add them to the list found here: http://www.alterawiki.com/wiki/new_qsys_issues
You'll save others some time and your input will be monitored by Altera as well. If you require assistance from Altera tech support please file a service request at this link: http://www.altera.com/mysupport
Honored ContributorThere used to be an EMIF SOPC Builder example that showed connecting a TI DSP up to an Altera FPGA but I'm not sure where it went. It sounds like you want your processor to use a more native solution using Avalon-MM (or maybe AXI if you have the latest version of Qsys installed). That memory tester design also works with .tcl running the host machine which controls all those tester blocks (instead of running software on the Nios II core). I was only suggesting to look at the master logic to see how it's structured and what sorts of things you need to do to ensure compliance with the Avalon-MM specification.
If you are not interested in verilog or C, are you looking for a VHDL and assembly coded sample? I guess I'm not really following what you are looking for because interfacing to other Avalon based cores is just a matter of following the Avalon specification when you define your interface. So if you have a customer processor it will have some sort of interface and you just ensure it conforms to Avalon-MM by adding a little glue logic if necessary.Honored ContributorI found myself an example here so I should be fine. I know that I had to follow the Avalon specification however I prefer an example so that I can be certain on how the implementation works.
Here is the example ftp://ftp.altera.com/up/pub/altera_material/11.1/tutorials/making_sopc_builder_components.pdfHonored ContributorSome general observations:
1) I don't recommend using chip select to qualify reads and writes (just use 'read' and 'write' for that) 2) That coding style probably doesn't scale to multiple registers very well. What I typically do is put the address decoding and byte enable and write qualification into one spot and when I need more register just replicate that one-liner. 3) For reads I wouldn't bother qualifying the byte lanes with enables, just register the entire word (master will have to filter out the unused byte lanes anyway...) For masters whenever possible try to decouple the control and data paths. For example if your master is capable of issuing multiple reads try to minimize the amount of control logic that captures the read data. In my various DMA master implementations I typically do this by using a FIFO and the only interaction between it and the control logic is that the FIFO full, empty, and used signals are used to throttle the control logic. You mentioned you were looking to do video, search for "Modular SGDMA Video" on alterawiki.com and you should find a dirt simple implemenation of a video pipeline that is capable of re-displaying frames when there are no more frames available to display (in video you have to keep displaying otherwise your display will loose sync).Honored ContributorModelSim and filename length limit
See this thread:- http://alteraforum.com/forum/showthread.php?t=37564Honored ContributorHi
I have a problem with the QSYS in Quartus II Version 13.1 When i generate my design the VHDL file is genarated. The problem is the assigments of the componenents greated by qsys are not all correct. It seems it randomly connects components. spipiggy : component LSA_version_2_spiCurrentDac timersupsolv3pump : component LSA_version_2_timerOutNdlWashPump uartusb : component LSA_version_2_uartEthernet is this a BUG ?Honored ContributorHi, I use Qsys a lot with same components which have different generics. On some configuartions I've error during synthesis with
error message which is coming from assertion in generated files: ... assert false report "Supplied generics do not match expected generics" severity Failure; I've googled for the error message and found exactly ONE site where this problem and ugly workaround are described. Is this issue fixed in newer Qsys versions? The site with problem description is here: http://flink-project.ch/multiple_subdevices_with_the_same_number_of_portsHonored ContributorHi alex
you may add some property to the parameter, e.g.: set_parameter_property <your parameter> AFFECTS_GENERATION false this should end up in also just one file for the different variations of your generics...Honored ContributorThank you for the hint. If this parameter is set to false, there is no "assert" statement generated for this parameter. If the parameter is the only one which is conflicting it solves the problem temporarily. This workaround also lasts only until next click on "Analaze Synthesis Files" in component editor: The _hw.tcl file is generated from scratch so all manual changes are lost.
In my opinion this is still a bug in Qsys: each instance must have own vhd file if instances have changes on parameters for which "assert" statements are generated.Honored ContributorIt would also be a good feature of component editor if this settings can be set by checkboxes in the "Parameters" tab and saved.
Honored ContributorUnsticking this thread since Qsys has been available for years.
