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Altera_Forum
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15 years ago

Qsys

As you find workarounds to Qsys issues please add them to the list found here: http://www.alterawiki.com/wiki/new_qsys_issues You'll save others some time and your input will be monitored by A...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi

I have a problem with the QSYS in Quartus II Version 13.1

When i generate my design the VHDL file is genarated. The problem is the assigments of the componenents greated by qsys are not all correct.

It seems it randomly connects components.

spipiggy : component LSA_version_2_spiCurrentDac

timersupsolv3pump : component LSA_version_2_timerOutNdlWashPump

uartusb : component LSA_version_2_uartEthernet

is this a BUG ?