Qsys

There used to be an EMIF SOPC Builder example that showed connecting a TI DSP up to an Altera FPGA but I'm not sure where it went. It sounds like you want your processor to use a more native solution using Avalon-MM (or maybe AXI if you have the latest version of Qsys installed). That memory tester design also works with .tcl running the host machine which controls all those tester blocks (instead of running software on the Nios II core). I was only suggesting to look at the master logic to see how it's structured and what sorts of things you need to do to ensure compliance with the Avalon-MM specification.

If you are not interested in verilog or C, are you looking for a VHDL and assembly coded sample? I guess I'm not really following what you are looking for because interfacing to other Avalon based cores is just a matter of following the Avalon specification when you define your interface. So if you have a customer processor it will have some sort of interface and you just ensure it conforms to Avalon-MM by adding a little glue logic if necessary.