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Altera_Forum's avatar
Altera_Forum
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13 years ago

QSYS Tri-State Conduit Pin Sharer

Hello,

I'm migrating a SOPC design to QSYS.

Doing so, I'm bumping into a problem.

In the design there is a tristate stage, where two Generic Tri-State Controllers (one for SRAM and the other for FLASH) are connected to a Tri-State Conduit Pin Sharer.

The Tri-State Conduit Pin Sharer should make sure the address and data pins for for SRAM and a FLASH device can be shared, while the control signals are kept separate.

However, something strange is happening.

If the address signals for the SRAM and FLASH DON'T share the same name in the Tri_state Conduit Pin Sharer, I'm able successfully run the "memory_test" software application from Eclips on the FLASH device. The SRAM is failing.

On the other hand, if the address signals for the SRAM and FLASH do share the same name in the Tri_state Conduit Pin Sharer, the FLASH device is failing(not able to open), while the SRAM is passig.

The data signal is using the same name in both cases.

Is anyone familiar with this issue?

Saber890

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    I think I may be having the same problem. I can't get the SRAM to work on a C3 dev kit using Qsys. If I write to the SRAM, I read the same value from everywhere in the SRAM space.

    I'll let you know if I find anything helpful. One thing I know is you have to set the address width of the flash and sram controllers in the component editor such that 2^addr_wdth = addr_space - i.e. don't set it to the actual physical address width of the bus.
  • Altera_Forum's avatar
    Altera_Forum
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    BTW, My problem turned out to be a bad board.

    My SRAM interface is working on a good board. The SSRAM comes up in asynchronous mode so the interface is a simple addr/data/cs/we/be/oe set of signals. As far a sharing goes. I used the name of the largest bus. I shared the Flash address name since the flash required 26 bits while the SRAM only required 23, whereas I shared the SRAM data bus name since it is a 32-bit bus while the flash is only 16.
  • Altera_Forum's avatar
    Altera_Forum
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    Hello,

    I havn't had much time to working with this issue lately,

    However, I was able to run the "Memory test" from Eclipse successfully on both the Flash and the SRAM devices when upgrading the SOPC design directly from the QSYS environment (thus creating a .QSYS file).The Tri-State Pin Sharer is using the same name for the address signals of the Flash and the SRAM devices.

    I did however, run into another issue. Inorder to clean up and remove unneccessary files from the project directory and change some file names (eg. <filename>_sopc to <filename>_qsys), I created a new project directory with a different name.

    In the new project folder, I added the toplevel file, the .QSYS file from the "old" project folder (the name of the .qsys file was also changed), and also I copy pasted the .QSF constraints into the new project folder's .QSF file.

    Doing, so I was no longer able to run the "Memory Test" SW application successfully on the Flash device. I could open the Flash device, but it seems it's failing when trying to use the "alt_flash_write" HAL function inorder to write to the Flash device. The SRAM test still runs successfully.

    If anyone know why the Flash device is failing when "importing" the .QSYS file into another project, please let me know.

    Saber890
  • Altera_Forum's avatar
    Altera_Forum
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    I had a further look into the issue,

    I took a .qsys file which was previously created in another QuartusII project and added it to a new project. I then renamed the .qsys file and generate the QSYS system.

    This way, I was able to successfully run the "Memory Test" SW application in Eclipse.

    After that, I go back to the QSYS design, and remove a pipeline stage which is placed infront of a clock crossing bridge.

    The clock crossing bridge further connects to the SYSID, JTAG_UART, UART and a PIO ip module.

    There is no direct connection between the clock crossing bridge and the flash/sram tristate stage.

    What happens now, is that the "Memory Test" for the Flash memory is failing(saying at least one test failed), while the SRAM is passing.

    So why is QSYS showing such strange behaviour?

    Saber890
  • Altera_Forum's avatar
    Altera_Forum
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    If you want to clean up your project. I suggest you do a project archive. This didn't used to work but it is working now (11.1sp2). (However, it doesn't change the name of anything. There seems to be no way to save a project under a new name without manually modifying all the file names!)

    We have some methods of starting fresh because Qsys seems to get corrupted with old settings and configurations. 1) try deleting the database folders - this is all of them except the software folder. 2) try restarting Qsys, 3)try rebooting your computer.

    I think archive will save some database folders but they aren't necessary.