Honored Contributor
Honored ContributorI had a further look into the issue,
I took a .qsys file which was previously created in another QuartusII project and added it to a new project. I then renamed the .qsys file and generate the QSYS system. This way, I was able to successfully run the "Memory Test" SW application in Eclipse. After that, I go back to the QSYS design, and remove a pipeline stage which is placed infront of a clock crossing bridge. The clock crossing bridge further connects to the SYSID, JTAG_UART, UART and a PIO ip module. There is no direct connection between the clock crossing bridge and the flash/sram tristate stage. What happens now, is that the "Memory Test" for the Flash memory is failing(saying at least one test failed), while the SRAM is passing. So why is QSYS showing such strange behaviour? Saber890
