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Altera_Forum's avatar
Altera_Forum
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14 years ago

Qsys not ready for general use yet

This is a word of warning. DO NOT waste your time trying qsys for any production system or if a deadline is involved. I have three different designs(one old and two new) that even if QSYS runs fine(not a given), then it won't boot from flash anyway. There is something in Qsys that prevents the EPCS device from booting properly. If you flash the sof from jtag, then it will run. It just won't boot. The same program boots fine if built with SOPC.

The second problem involves memory. In SOPC you could create any size memory that you needed and do anything to the output lines to make it work with the address and select lines(ie combine them to create address/device selectors) Under qsys you can no longer do this. All outside lines must go to pins with no logic in between.

OK fine, I can live with that and create multiple memories. Now in the eclipse software you can not combine multiple memories for a contiguous memory region. So your stack and heap must be assigned to only one small memory even though under SOPC you could make this one large memory and have complete use of it all.

I could probably make my own memory controller, but given all the other QSYS limitations and problems this is not worth my time to debug an ALPHA product. I will wait until it will hopefully get fixed before they take SOPC away.

And yes, Altera support has no solution other than don't do this- it is unsupported. It is supported in SOPC, but not in the replacement??

Don't waste your time with qsys, unless you have time to waste.

Dan

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    i am not sure what your flash woes are caused by, but that said i have a few comments.

    i dont understand what you mean by

    "In SOPC you could create any size memory that you needed and do anything to the output lines to make it work with the address and select lines(ie combine them to create address/device selectors) Under qsys you can no longer do this. All outside lines must go to pins with no logic in between."

    and i definitely disagree that "All outside lines must go to pins with no logic in between." could you elaborate?

    "Now in the eclipse software you can not combine multiple memories for a contiguous memory region." This statement is just wrong. you can create any memory region you want in the linker script as long as the memories consist of a contiguous memory blocks. This was true for SOPC Builder generated projects as well. this can be done in the bsp editor, or with custom linker scripts.

    thanks,

    Dalon
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    If you're not using Nios, then basically you can do _almost_ everything with HDLs. Even for things like Flash read/write, and IPs that don't use the Avalon bus, you're basically good to go with HDL and/or BDF. There are certain IPs (e.g. Nios) that requires you to use Qsys. I try and avoid situations like these as much as possible. For example, if I can replace a Nios function by rewriting it in HDL, I will do so (provided the function/feature isn't too complex, and I have the time). Same with all the other IPs that require the use of Qsys.

    To me, Qsys doesn't give the customer any visibility of your design in a HDL format. Every small change you want to make will have to go through the Qsys tool, which makes it troublesome (at least to me). The top-level VHDL file that I asked Qsys to generate does not give me any visibility over the underlying sub-systems... another reason why I try to stay away from Qsys.

    This of course will change if Altera makes changes to their Qsys to be able to generate HDL files that gives the customer enough visibility as to which subsystems they are using, and how each of the subsystems are interconnected.

    I haven't tried exporting all the subsystems ports (this may give me the visibility I want), but that again is more of a hack than a real solution.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    This is a word of warning. DO NOT waste your time trying qsys for any production system or if a deadline is involved. I have three different designs(one old and two new) that even if QSYS runs fine(not a given), then it won't boot from flash anyway. There is something in Qsys that prevents the EPCS device from booting properly. If you flash the sof from jtag, then it will run. It just won't boot. The same program boots fine if built with SOPC..

    --- Quote End ---

    Is it still true for QSys 12.1 sp1 ?
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    Is it still true for QSys 12.1 sp1 ?

    --- Quote End ---

    It has never been true.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    It has never been true.

    --- Quote End ---

    Yes, this was quite true for since qsys first came out. I kept trying each version as it was released. Finally on 12.1 it magically worked! No one ever admitted that it was broken, but no one could ever show me a board that worked with the epcs. Then one day it just worked with no change to my files, other than recompiling with version 12.1. Typical not a problem...not a problem....oh, yes we fixed that "issue"..... ;)

    So yes, it is safe to use qsys now, as long as you can live with it's other issues. I would skip directly to SP1 though. 12.1 by itself was very buggy and crashed when ever you had the signal tap up. It was identified and fixed in sp1 though. I haven't had a crash yet.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    So yes, it is safe to use qsys now, as long as you can live with it's other issues.

    --- Quote End ---

    Hello, imported_dan !

    What other issues still exist in QSys 12.1 sp1?
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hello,

    I also share your frustrations with Qsys.

    It works ok when designs are fairly simple. As soon as you start adding complex cores like 2'nd DDR3 memory controller, multiple transceiver channels, PCI Express, multiple masters, Qsys hierarchies, etc., things simply break.

    I've been working a lot with Qsys since Quartus 10.x. Some problems get fixed, some don't, and new problems get introduced.

    My approach is to keep the Qsys simple. For complex cores, just use MegaWizard flow, and add those cores outside. Then connect them to Qsys using Avalon Bridge.

    Thanks,

    Evgeni
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    I also share your frustrations with Qsys.

    It works ok when designs are fairly simple. As soon as you start adding complex cores like 2'nd DDR3 memory controller, multiple transceiver channels, PCI Express, multiple masters, Qsys hierarchies, etc., things simply break.

    --- Quote End ---

    Please explain in more detail - how breaking looks like?
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    "Breaking" takes different shapes and forms: conversion from SOPC, synthesis failures, fit failures, simulation failures. Here is the list of Qsys-related service requests I opened in the last couple of years (serious ones, things I couldn't work around). I'll be happy to provide detailed description.

    10893169 *_ddr3_emif_0_p0_pin_assignments.tcl script doesn't generate constraints for the second DIMM

    10912653 Error "Number of lanes 8 out of range (1,0) when migrating to Qsys 12.1

    10892096 Error when trying to generate Qsys system of tt_qsys_design example

    10891664 Qsys component exports incorrect address range

    10892045 Error during qsys simulation generation

    10892022 Synthesis error during Qsys system compile

    10891631 Error during qsys generation

    10886678 Example DDR3 UniPHY megawizard design fails synthesis

    10886673 Modelsim simulation of ddr3 qsys fails

    10883794 Failure to open DDR3 UniPHY Qsys example

    10854315 Migrating from SOPC to Qsys

    10848911 Error during quartus fit