Qsys not ready for general use yet

If you're not using Nios, then basically you can do _almost_ everything with HDLs. Even for things like Flash read/write, and IPs that don't use the Avalon bus, you're basically good to go with HDL and/or BDF. There are certain IPs (e.g. Nios) that requires you to use Qsys. I try and avoid situations like these as much as possible. For example, if I can replace a Nios function by rewriting it in HDL, I will do so (provided the function/feature isn't too complex, and I have the time). Same with all the other IPs that require the use of Qsys.

To me, Qsys doesn't give the customer any visibility of your design in a HDL format. Every small change you want to make will have to go through the Qsys tool, which makes it troublesome (at least to me). The top-level VHDL file that I asked Qsys to generate does not give me any visibility over the underlying sub-systems... another reason why I try to stay away from Qsys.

This of course will change if Altera makes changes to their Qsys to be able to generate HDL files that gives the customer enough visibility as to which subsystems they are using, and how each of the subsystems are interconnected.

I haven't tried exporting all the subsystems ports (this may give me the visibility I want), but that again is more of a hack than a real solution.