Honored ContributorHi, I am currently working on an Avalon memory master that requires the readdatavalid signal to properly function. I set up the signal in QSYS but when I observed the Signaltap output for a memory read, I noticed that the readvalidsignal is always 0. Is there any reasons that can cause this? I can provide a screenshot of the signaltap output if requested.
Honored ContributorDid you declare that the avalon master would use pipelining? It is possible that QSys would only generate the logic behind the read data valid signal when the "Maximum pending read transactions" parameter is 0.
Honored ContributorHonored ContributorSorry I should have re-read my answer... I meant only if the parameter is not 0. When 0 it basically means there is no pipelining and the read data valid signal isn't needed. Try to set it to another value (ideally to the highest number of transactions you plan to have before getting a read value back) and see if the signal becomes valid.
Honored ContributorThe signal is still not asserted for some reason
Honored ContributorAre you sure that you are reading from a valid address? Could you do a signaltap capture of the signals on both the master and the slave, to check that the slave is receiving the read request ans replying?
