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Altera_Forum's avatar
Altera_Forum
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13 years ago

QSYS ignores readdatavalid signal

Hi, I am currently working on an Avalon memory master that requires the readdatavalid signal to properly function. I set up the signal in QSYS but when I observed the Signaltap output for a memory re...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Are you sure that you are reading from a valid address? Could you do a signaltap capture of the signals on both the master and the slave, to check that the slave is receiving the read request ans replying?